1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, an improvement in the semiconductor device capable of increasing a rate of an effective packaging area which is represented by a ratio of a semiconductor device chip area to a packaging area of a packaging substrate such as a printed-circuit board, in which the semiconductor device is packaged.
2. Description of the Prior Art
In general, a configuration shown in FIG. 1 has been used as a semiconductor device in which a transistor device is formed on a silicon substrate. A reference 1 denotes a silicon substrate; 2, an island such as a heat radiation board on which the silicon substrate 1 is mounted; 3, a lead terminal; and 4, a sealing plastic.
As shown in FIG. 1, the silicon substrate 1 on which the transistor device is formed is secured with a brazing filler metal 5 such as solder to the island 2 such as a copper-based heat radiation board to be mounted thereon. A base electrode and an emitter electrode of the transistor device are electrically connected via bonding wires to respective lead terminals 3 which are arranged in the neighboring area of the silicon substrate 1. The lead terminal 3 to be connected to a collector electrode is formed integrally with the island 2. The silicon substrate 1 is electrically connected to the island 2 by mounting the silicon substrate 1 on the island 2, and then the silicon substrate 1 and a part of the lead terminal 3 are molded by a thermoset plastic 4 such as epoxy resin in terms of transfer molding.
Usually such plastic-molded semiconductor device is packaged on the packaging substrate such as a glass epoxy substrate and is then electrically connected to other semiconductor devices or circuit elements which are mounted on the same packaging substrate. A resultant semiconductor device is then treated as a single parts to carry out a predetermined circuit operation.
FIG. 2 shows a sectional profile of the semiconductor device in the prior art when the semiconductor device is packaged on the packaging substrate. A reference 20 denotes a semiconductor device; 21, 23, lead terminals for the base and emitter electrodes; 22, a lead terminal for the collector electrode; and 30, a packaging substrate.
A packaging area of a packaging substrate 30 in which the semiconductor device 20 is packaged can be represented by a region which is surrounded by the lead terminals 21, 22, 23 and conductive pads connected to these lead terminals 21, 22, 23. Such packaging area is large in contrast to the silicon substrate (semiconductor chip) area in the semiconductor device 20. Most of the packaging area is occupied by molding plastic and the lead terminals rather than the semiconductor chip area which effects actually a preselected function.
If a ratio of the semiconductor chip area having the actual preselected function to the packaging area is now defined as a rate of an effective packaging area, it can be understood that such rate of the effective packaging area is extremely low in the plastic-molded semiconductor device. A low rate of the effective packaging area indicates the presence of a large dead space which is not directly concerned with the packaging area of the semiconductor chip, most of the packaging area of the semiconductor chip being used to execute a preselected function. Such large dead space prevents the packaging substrate 30 from being formed with high density and miniaturized.
In particular, this problem remarkably occurs in the semiconductor device having a small package size. For instance, as shown in FIG. 3, a size of the semiconductor chip (SC-75A) based on the EIAJ standard is 0.40 mm.times.0.40 mm at its maximum. When the semiconductor chip is plastic-molded as shown in FIG. 1, an overall size of the semiconductor device is 1.6 mm.times.1.6 mm. Hence, the chip area of the semiconductor device is 0.16 mm.sup.2 and the packaging area on which the semiconductor device is packaged is 2.56 mm.sup.2 if the packaging area is assumed to be substantially identical to the area of the semiconductor device. Therefore, a rate of an effective packaging area of the semiconductor device becomes about 6.25%. This means that most of the packaging area is occupied by the dead space having no direct connection with the semiconductor chip area which is used to execute the preselected function.
With respect to the packaging substrate for use in various recent electronic devices, e.g., portable information processing unit such as personal computer, electronic pocketbook, etc., 8 mm video camera, portable telephone, camera, liquid crystal television, and the like, packaging substrates employed in such electronic devices tend to be formed with high density and miniaturized with the progress of miniaturization of the main body of electronic devices.
However, in the above semiconductor device, reduction in size or miniaturization of the packaging substrate is prevented by such large dead space.
As a prior art showing an improvement in a rate of an effective packaging area, there has been a Patent Application Publication (KOKAI) 3-248551 (see FIG. 4). In this prior art reference, in order to reduce the packaging area as much as possible, such a technique has been set forth that lead terminals 41, 42, 43 which are connected respectively to base, emitter, and collector electrodes of a semiconductor chip 40 are formed not to protrude outwardly from side surfaces of the plastic mold 44 and to constitute identical surfaces to the side surfaces of the plastic mold 44.
According to this configuration, the packaging area can be made small because top end portions of the lead terminals 41, 42, 43 do not project outwardly, but a size of the dead space cannot be so improved as it would be expected.
In the above semiconductor device, there have been such problems that a wire connecting step and an injection molding step for the molding plastic are needed to thus make a material cost higher and to make manufacturing steps complicated, and as a result a production cost cannot be reduced.
In order to increase a rate of an effective packaging area at its maximum, if the semiconductor chip is packaged directly on the packaging substrate, as described above, a rate of an effective packaging area can be maximized.
Meanwhile, as a prior art showing packaging of the semiconductor chip on the substrate such as the packaging substrate, a flip-chip technique has been well known wherein a flip-chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is bonded to a packaging substrate 47 in terms of face down bonding, for example, as shown in a Patent Application Publication (KOKAI) 6-338504 (see FIG. 5). Usually, this prior art has been mainly applied to a lateral semiconductor device such as MOSFET, etc. with relatively small heat generation, wherein a gate (base) electrode, a source (emitter) electrode, and a drain (collector) electrode are formed on the same principal surface of the silicon substrate and current or voltage paths are formed in the lateral direction.
However, in a vertical semiconductor device like a transistor device, etc. wherein a silicon substrate serves as one of electrodes and respective electrodes are formed on a different surface so that current paths are formed in the vertical direction, it is difficult to employ the above flip-chip technique.